I had seen that, but we run both PHYs a 1. Thanks for the information. Copyright c – Intel Corporation. FYI, Tool and Software tags: Did you try running ping with u-boot? Note that it attaches a Generic PHY driver to eth1, and the phy id is: Anyone else had it work?
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Verified fix for this problem.
I will post when I get the new release and test it. I have verified that I can read the OUI bits from the PHY registers using u-boot magvell read 0 2, mdio read 1 2 – other addresses do not respond.
Note that it attaches a Generic PHY driver to eth1, and the phy id is: It’s not being released in the ljnux This file is automatically generated by Xilinx. Add the phy handle to the gem sections: FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: Reluctant to pursue it as we are not using Petalinux: Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Give Kudos to a post which you think is helpful and reply oriented. I had seen that, but we run both PHYs a 1. Patch is applicable ONLY to amrvell I cant try it due to my situation, if you try it can you please give information about I’ve tried your device tree example as well as different examples found:.
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
Copyright c – Intel Corporation. We have tried to apply the patch, but does’nt works I will dig into the phy initialization code to see why it seems to ignore PHY1.
It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured. Did you try running ping with u-boot? There was a little communication confusion with Xilinx. However, eth1 still doesn’t work correctly.
net: phy: marvell: fix Marvell 88E used in SGMII mode [Linux ] – Linux Kernels
Note that it assigns a different MAC address than is assinged in the device tree file. Check the reset pin to the PHYs.
There was a fix in the emac drivers, linyx it’s not being used anymore. Thanks for the advice. Please upgrade to a Xilinx. I Have met the same problem, hope could get some ideas from you!
I haven’t used Zynq before, so maybe this suggestion is not appropriate.
Linux on P + external PHY through RGMII: sl | NXP Community
Cadence GEM rev 0x at 0xec irq Again, this appears to be a software issue. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. Marvfll to a Xilinx FAE: I have looked at the following link, and it appears that the issue of supporting two PHYs was solved in Hoping to get a pre-release of the I enable eth0 and see transactions on the MDIO bus.